This application claims priority from Korean Application No. 2001-30522, filed May 31, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having clocks with a selectable period and methods for using the same.
It is well known to store data in integrated circuit memory devices, including memory devices that store the data as an electric charge in a capacitor. Such memory devices typically refresh the stored data as the electrical charge may otherwise be lost, for example, due to leakage currents from a capacitor. One known approach is called a refresh operation in which the stored data is completely erased and the data is repeatedly retrieved and rewritten. An example of such a device is a dynamic random access memory (DRAM). DRAMs of this type generally cannot be accessed during the refresh operation. The time during which a DRAM cannot be accessed during the refresh operation is generally called a busy rate. It is preferable to have the busy rate as short as possible.
It is also known to provide computer systems or other devices including such DRAM with a sleep mode in which much of the electronic circuitry of the computer system is turned off to reduce power consumption. However, DRAMs of the type described above are generally not turned off because they typically need to be continuously refreshed to maintain data. Therefore, a self-refresh current generally is allowed to flow through the DRAMs even during the sleep mode of the computer system. As a result, it is desirable to reduce the self-refresh current, especially where the computer system is battery operated.
Various approaches have been suggested to reduce the self-refresh current flowing in a DRAM. One such approach is to change the refresh period of the DRAM based on the temperature of the DRAM where the temperature is divided into several ranges. More particularly, a comparatively lower period of a refresh clock may be used at a lower temperature as, typically, at a lower temperature, the DRAM is able to retain data for a longer time.
One problem with the changing of the refresh period is that the characteristics of the temperature sensor used to determine the device temperature may change significantly due to variations during manufacture of the temperature sensor. As a result, erroneous temperature measurements may be provided for the DRAM. For example, a DRAM may be operating at 60xc2x0 C., thus needing a relatively high-frequency refresh clock, but the temperature sensor may erroneously detect the temperature as 45xc2x0 C. and select a low-frequency refresh clock. In this case, refresh errors may occur, possibly resulting in lost data. While the problem of temperature sensor variability may be reduced by the use of higher performance sensors, doing so typically will result in an increase in the size of the temperature sensor. Furthermore, other manufacturing process introduced variations in the DRAM may change the length of time the DRAM is able to retain data at various temperatures. In addition, to these sources of variability, a DRAM cell may become excessively deteriorated over time and some or all of the DRAM cell may fail to refresh successfully, potentially causing the computer system to experience a refresh malfunction for the entire DRAM cell.
Embodiments of the present invention include clock generation circuits for an integrated circuit device including a temperature sensor circuit, the temperature sensor circuit including a calibration circuit responsive to a temperature coding signal and a temperature sensor. The temperature sensor circuit has a first or test mode state in which a temperature output signal of the temperature sensor circuit is based on a temperature sensor output control signal and a second or normal mode state in which the temperature output signal is based on the temperature sensor and the calibration circuit. A clock period controller circuit includes a calibration circuit responsive to a period coding signal. The clock period controller circuit generates a period control signal based on the temperature output signal and the calibration circuit of the clock period controller circuit. A clock generator circuit generates a clock signal based on the period control signal.
In further embodiments of the present invention, the calibration circuit of the temperature sensor circuit includes a plurality of fuses and the temperature coding signal selects the state of the plurality of fuses to calibrate the temperature output signal relative to an output of the temperature sensor. The calibration circuit of the clock period controller circuit may also include a plurality of fuses and the period coding signal may select the state of the plurality of fuses to calibrate the period control signal.
In other embodiments of the present invention, the state of the temperature sensor circuit is selected based on the temperature sensor output control signal. The temperature output signal may be a digital signal having a plurality of states, ones of which correspond to temperature operating ranges of the integrated circuit device. The first state may be a test mode and the second state may be a normal operating mode. The temperature sensor output control signal may include a plurality of bits that designate ones of the temperature operating ranges in the test mode. The digital temperature output signal indicates a detected temperature of the integrated circuit device. The temperature sensor circuit may also include a multiplexer that outputs the temperature output signal based on the digital temperature signal from the temperature sensor and the temperature coding signal.
In further embodiments of the present invention, the clock period controller circuit includes a plurality of period controllers calibrated by the calibration circuit of the clock period controller circuit based on the period coding signal. One of the plurality of period controllers is selected by the temperature output signal to generate the period control signal. The clock generator circuit may include an oscillator that generates the clock signal with a period based on the period control signal. The integrated circuit device may be a memory device and the clock signal may be a refresh clock.
In other embodiments of the present invention, integrated circuit memory devices are provided including a temperature sensor circuit including a calibration circuit responsive to a temperature coding signal and a temperature sensor that generates an operating temperature signal responsive to a temperature of the memory device and the calibration circuit. The temperature sensor circuit has a first state in which a temperature output signal of the temperature sensor circuit is based on a temperature sensor output control signal and a second state in which the temperature output signal is the operating temperature signal. The first state or the second state is selected by the temperature sensor output control signal. A clock period controller circuit, including a calibration circuit responsive to a period coding signal, generates a period control signal based on the temperature output signal and the calibration circuit of the clock period controller circuit. A clock generator circuit generates a refresh clock of the memory device based on the period control signal. The operating temperature signal and the temperature sensor output control signal each may include a plurality of bits, ones of which correspond to temperature operating ranges of the memory device.
In further embodiments of the present invention, methods are provided for controlling the refresh period of an integrated circuit memory device. A temperature sensor circuit of the memory device is calibrated to generate an operating temperature signal corresponding to an operating temperature of the memory device by inputting to the temperature sensor circuit a selected temperature coding signal. A test mode of the temperature sensor circuit is selected in which a temperature output signal of the temperature sensor circuit is based on a temperature sensor output control signal or a normal mode of the temperature sensor circuit is selected in which the temperature output signal is the operating temperature signal. The first state or the second state is selected by the temperature sensor output control signal. A clock period controller circuit of the memory device is calibrated to generate a period control signal having a desired period by inputting to the clock period controller circuit a period coding signal, the period control signal further being based on the temperature output signal. A refresh clock of the memory device is generated, the period of the refresh clock being based on the period control signal.